The present invention is directed generally to integrated circuits and their fabrication, and more specifically to a redundant circuit configuration that functions to improve the production yield of integrated circuits, making feasible the formation of a single "macro-circuit" on an entire silicon wafer (hereinafter "wafer scale integration").
As used herein, the terms "redundant" or "redundancy" are used in their normal sense to refer to extra copies of a circuit. However, it is recognized that these terms enjoy a specialized meaning in the field maintenance and reliability of digital systems: A circuit is said to be redundant (or has redundancy) if there is no test available for detecting a particular fault. As will be seen, this latter meaning could apply in a general sense to the present invention. However, unless indicated otherwise, interpretation herein of the terms redundant and/or redundancy should be made as if they were used in their normal sense.
Recent advances in the field of semiconductor fabrication have resulted in an integrated circuit technology capable of providing large amounts of electronic circuitry in a very small package. The advantages of constructing electronic systems from integrated circuitry often include a savings in cost, size, weight, and power consumption when compared to a similar system constructed from discrete components. A further advantage includes realization of a high circuit speed within the integrated circuit itself since signals will not be slowed down as they would when moving from package to package. In addition, a fully-tested, operable integrated circuit provides increased reliability over a similar configuration of discrete devices, resulting in reduced maintenance costs to the ultimate user.
These advances have, in part, concentrated on increasing integrated circuit fabrication "yield" (the number of operable circuits per fabrication run), either by reducing the density of defects in a "wafer" (the silicon substrate upon which an integrated circuit is formed) or by reducing the dimensions of the circuit "die" (that area of the wafer used to form each individual circuit). At present, defects in a wafer cannot be avoided during integrated circuit fabrication, and a single defect can ruin an entire circuit. As one might expect, the larger the die that forms the circuit the greater chance for a defect to appear and render the circuit inoperative. Yield, therefore, decreases as the size of the die increases, both because there are fewer places on a wafer for larger die and because larger circuits are more likely to incorporate a defect and be rendered useless. Thus, if too much electronic function is packed into a circuit, the large size of the die required to form the circuit would result in such a low yield per wafer that the cost per circuit may become prohibitive.
A typical electronic system contains both large-scale and medium-scale integrated circuits, and the cost of designing and constructing the system rises rapidly as the number of individual circuits increases. When a large number of discrete, less powerful, cheaper circuits are used to construct the system, testing and assembly costs tend to build up. To minimize the total cost of the system one would like ideally to use either a small number of very powerful and complex integrated circuits. Not only are labor costs reduced, but this would provide the system with the high speed, small size, reduced weight and low power-consuming advantages of integrated circuit technology. Again, however, if too much electronic function is packed into a circuit, as mentioned above, the large size of the die may result in such a low yield per wafer that the cost per circuit would become prohibitive.
Thus, it can be seen that while it is extremely desirable to put as much circuit function as possible into a single microelectronic circuit, the larger die size resulting from the increased function may so reduce the yield as to limit very large-scale, much less wafer-scale, integration.